Heavy capacitive loads are very common in industrial and commercial systems and equipment. A common example is a piezoelectric element which is used extensively in such applications as ink jet printers, speakers and motor drives. A piezoelectric element, formed by piezoelectric material sandwiched between two electrodes, is typically electrically modeled as a large capacitor, with the piezoelectric material acting as both a dielectric between the electrodes and an actuator under the influence of the electric field resulting from the application of a voltage across the electrodes. Indeed, an entire matrix of piezoelectric actuators for individual droplet making mechanisms in an inkjet printer head may be modeled as a single capacitive load. Throughout this application, unless otherwise expressly stated, discussion of a capacitive load in the form of a piezoelectric actuator will be understood to also include a matrix of such actuators producing a single capacitive load to which an output voltage is applied, and that this capacitive load also has typically resistive and inductive components to it.
The electrical drive to the capacitive load such as a piezoelectric actuator may be a controlled high voltage waveform delivered, as an example, once per cycle of printer head operation or the like. The shape, period and frequency of this waveform can be heavily dependent upon the application. Most piezoelectric element drive waveforms have fast switching transitions. There may also be a need for a portion of the waveform to exhibit finer linearity control and timing control, such as when the droplet is actually formed in the output of the respective ink jet printer ink jet nozzle and sized as it is ejected at a finely controlled time. Improvements in the ability to control these parameters are always in need to enhance such things as printer performance.
Therefore, typically a fast linear high voltage (HV) amplifier is used to deliver the waveform to the piezoelectric element. In such a fast linear high voltage (HV) amplifier, power dissipated while switching a load capacitor between a low voltage, such as a ground voltage GND (e.g., a zero voltage) to the high voltage VDD (as an example 50V) is given by:Pdiss=CL×VDD2×·f  (1)where CL=Load Capacitor capacitance, f=Frequency of drive waveform.
Existing linear capacitive load drives conform to equation 1. This relationship can result in limitations on attributes of the application or engineering system, such as maximum load capacitance and frequency of the waveform. This relationship can further limit the number of actuators that can be driven, such as in the piezoelectric inkjet printer print head application, the number of inkjets and thereby the resolution of the printing by the print head, as well as the speed of printing, i.e., cycles per second of actuation. Achieving higher resolution and higher frequency of the drive voltage waveform is generally desirable. In inkjet printer piezoelectric applications, faster operation is always a goal resulting in faster printing speed.
FIG. 3 is an example of a conventional high capacitive load drive circuit 140, utilizing a single amplifier, which may be like a PA78, PA79, PA86, PA69 or PA243 amplifier, available from applicants' assignee Cirrus Logic. The circuit 140 may have a class B gate drive amplifier 142 utilized to drive a load capacitor 132 (“CLOAD”), connected to ground 170. The amplifier 142 may have a negative input 152, which is connected to ground 170 through a resistor 156, such as a 1K ohm resistor and connected to the output through a resistor 169 such as a 9K resistor. The amplifier 142 may have a positive input 150 connected to an input voltage 153, which may be an arbitrary drive voltage waveform which is, in turn, connected to ground 170.
The amplifier 142 may have a HiGate output 178 connected to the gate of an external high power PFET 176, and a LoGate output 174 connected to the gate of an external high power NFET 172. The amplifier 142 may be implemented on an integrated circuit, and “external” means that the PFET and NFET may be, but need not necessarily be, implemented in a separate integrated circuit and packaged separately (“external”) to the amplifier 142, depending on the current drive required for the capacitive load. The source of the PFET 176 may be connected through a resistor 151, such as a 0.1 ohm resistor, to a high voltage source 180, such as a 50 V source V50, in which the high voltage source 180 is, in turn connected to ground 170. The source of the NFET 172 may be connected to ground 170 through a resistor 171, such as a 0.01 ohm resistor for current sense. The drains of the PFET 176 and NFET 172 are connected to the load capacitor CLOAD 132, such as a 527.4 nF capacitor. It will be understood that as high power integrated circuit technology advances, it may become possible to integrate more of or even all of the circuitry described in this application and related appropriate and necessary circuitry on a single integrated circuit so that “external” power FETs and the like need no longer be “external.”
The output node of the amplifier connected to the load capacitor 132 may also be feed back to the negative input 152 of the amplifier 142 through a parallel RC arrangement containing a resistor 169, such as a 9 K ohm resistor and a capacitor 168, such as a 40 pF compensation capacitor, in parallel with resistor 169. The closed loop gain of the amplifier 142 is set by the resistive divider network comprised of resistors 169 and 156.
The amplifier 142 may have a +VS connection 148 to a high voltage supply 180, such as a 50 V supply, which voltage supply 180 is also connected to ground 170. The voltage supply 180 is also connected to the source of the PFET 176 through the resistor 151. The amplifier 142 may also have a connection 149 to a voltage supply 144, such as a 12 V voltage supply, also connected to ground 170 to set the gate drive voltage. The amplifier 142 may also have a −VS connection 143 connected to ground 170 and a GND connection 145 connected to ground 170, along with a VG connection to a voltage supply 144, such as a 12 V voltage supply also connected to ground 170.
In operation, the HiGate output 178 of the amplifier 142, in response to the rising portion of the input 153, controls the voltage applied to the gate of the PFET 176 which controls the current flow through the PFET 176 to the load capacitor 132 and, in response to the falling portion of the input voltage 153, controls the gate of the NFET 172 to regulate the current flow from the CLOAD capacitor 132 as the CLOAD capacitor 132 discharges to ground during a ramp down period. The load capacitor CLOAD 132 thus charges up to from 0V to VS (e.g., 50 V) during the ramp up and discharges from 50V to 0V during the ramp down, assuming ground is 0V.
The disadvantages to such operation with a single amplifier 142 are as noted, namely, that the amplifier 142 exhibits high power dissipation and high cost. For piezoelectric inkjet printer applications, this disadvantage limits the resolution of printing and the speed of printing. Applicants have found that a better design according to aspects of the disclosed and present invention can reduce power dissipation in the drive circuit and save cost for the application.
Adiabatic switching (between rail high or low voltage and the other rail voltage in sequential rails) has been employed in digital circuits at low voltages as indicated in the following references. Indermaur et al., Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design, IEEE Symposium on Low Power Electronics (1994), relates to charge recovery through adiabatic switching for power reduction in CMOS integrated circuits. Gabara, Pulsed Power Supply CMOS—PPS CMOS, IEEE Symposium on Low Power Electronics (1994), relates to similar ramped driving and charge recovery, called “pulsed power” in CMOS circuits. Similarly Svensson et al., Driving a Capacitive Load Without Dissipating fCV2, IEEE Symposium on Low Power Electronics (1994), describes a similar “stepwise charging” in CMOS circuits.
FIG. 6 shows a schematic diagram of a circuit 310 useful in understanding energy dissipation while driving a capacitive load CLOAD 320. FIG. 6 shows two switches 322, 324 for charging and discharging the capacitor CLOAD 320. The circuit 310 includes a voltage supply 326, such as a 50 V DC power supply VDD, which when voltage controlled switch 322 is closed charges the load capacitor 320 through a resistor 328 that is modeling the on resistance of switch 322, and a voltage controlled switch 324, which, when closed, discharges the load capacitor 320 through a resistor 330 to ground. Each of the switches 322, 324 has a respective switch voltage supply 340, 342 to assist in the control of the timing and operation of the respective switches.
FIG. 6 shows switch 322, that when closed charges the load capacitor 320 with a charge Q=CLOAD×VDD. The energy from the supply 326 to provide this charge is ESUPPLY=Q×VDD=CLOAD·VDD2. The energy stored in the capacitor 320 is EC=CLOAD×VDD2/2. These results can also be derived by integrating the instantaneous power over the period of interest.
                                          E                          S              ⁢                                                          ⁢              U              ⁢                                                          ⁢              P              ⁢                                                          ⁢              P              ⁢                                                          ⁢              L              ⁢                                                          ⁢              Y                                =                    ⁢                                    ∫              0              ∞                        ⁢                                                                                i                                          V                      ⁢                                                                                          ⁢                      D                      ⁢                                                                                          ⁢                      D                                                        ⁡                                      (                    t                    )                                                  ·                                                      V                                          D                      ⁢                                                                                          ⁢                      D                                                        ⁡                                      (                    t                    )                                                              ⁢                                                          ⁢                              ⅆ                t                                                                                  =                    ⁢                                    C              L                        ·                          V                              D                ⁢                                                                  ⁢                D                                      ·                                          ∫                0                ∞                            ⁢                                                          ⁢                                                                    ⅆ                                          V                                              O                        ⁢                                                                                                  ⁢                        U                        ⁢                                                                                                  ⁢                        T                                                                              ·                                      ⅆ                    t                                                                    ⅆ                  t                                                                                                  =                    ⁢                                    C              L                        ·                          V                              D                ⁢                                                                  ⁢                D                                      ·                                          ∫                0                50                            ⁢                              ⅆ                                  V                                      O                    ⁢                                                                                  ⁢                    U                    ⁢                                                                                  ⁢                    T                                                                                                                    =                    ⁢                                                    C                L                            ×              50              ×              50                        =                          2500              ·                              C                L                                                                                                  E            C                    =                    ⁢                                    ∫              0              ∞                        ⁢                                                            i                  dd                                ⁡                                  (                  t                  )                                            ·                                                v                  out                                ⁡                                  (                  t                  )                                            ⁢                                                          ·                              ⅆ                t                                                                                  =                    ⁢                                    C              L                        ·                                          ∫                0                ∞                            ⁢                                                          ⁢                                                                    ⅆ                                                                  v                                                  O                          ⁢                                                                                                          ⁢                          U                          ⁢                                                                                                          ⁢                          T                                                                    ⁡                                              (                        t                        )                                                                                                  ⅆ                    t                                                  ·                                                      V                    OUT                                    ⁡                                      (                    t                    )                                                  ·                                  ⅆ                  t                                                                                                  =                    ⁢                                                    C                L                            ·                                                [                                                            v                                              O                        ⁢                                                                                                  ⁢                        U                        ⁢                                                                                                  ⁢                                                  T                          2                                                                                      2                                    ]                                0                50                                      =                          1250              ·                              C                L                                                                    E              diss        ⁢                                  ⁢        1              =        ⁢                            E                      S            ⁢                                                  ⁢            U            ⁢                                                  ⁢            P            ⁢                                                  ⁢            P            ⁢                                                  ⁢            L            ⁢                                                  ⁢            Y                          -                  E          C                    =              1250        ·                  C          L                    
This analysis shows that half of the energy supplied by the voltage source is stored in the load capacitor while the other half is dissipated in switch 322 and resistor 328. During the discharge phase the charge is removed from CLOAD 320 and the energy is dissipated in switch 324 and resistor 330. Thus the energy dissipated during each switching cycle is given by:Ediss=CLOAD·VDD2=2500·CLOAD(VDD=50 V)  Equ (1)
While existing systems are of great benefit, there is need to improve performance of capacitive load drive systems, such as piezoelectric drive systems, including through energy savings, improved speed of operation, and the ability to drive more load elements, such as more piezoelectric elements. Advantageously the resolution of inkjet printers can be improved according to aspects of embodiments of the present invention present invention.